RISC stands for "Reduced Instruction Set Computer".
A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer, or CISC).
Features which are generally found in RISC designs are uniform instruction encoding (e.g. the op-code is always in the same bit positions in each instruction which is always one word long), which allows faster decoding; a homogenous register set, allowing any register to be used in any context and simplifying compiler design; and simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions.
Examples of (more or less) RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based RISC System/6000 and SP/2 lines. Seymour Cray's vector machines are arguably RISC processors.
The driving forces behind RISC are:
- It's easier to design and build a fast processor if it only has to support relatively few instructions
- The state-of-the-art in creating compilers is such that it is now possible to generate code that uses the more general-purpose instructions present in a RISC processor (versus a more simple compiler that relies on the existence of many specialized instructions in a non-RISC processor).
This can be summed up as "With RISC, the hardware is dumb and fast, and the compilers are smart and slow".
There are a number of differences between 'typical' pre-RISC ISAs and 'typical' RISC ISAs. One of these is the "brancy delay slot": an instruction immediately following a jump or branch, which capitalizes on the fact that the processor may take more than one cycle to complete the jump instruction, and allows the program's implementor to use the lookup time more efficiently.
Based on a FOLDOC entry